Introduction to Intel Phi workshop

This year a new technology will land on the New Zealand eScience Infrastructure resources. The Intel Xeon Phi is the first coprocessor designed for HPC purposes and it opens a new era of challenging strategies in parallel programing.

The Intel Xeon Phi coprocessor is suited for massive parallel applications that feature a high ratio of computation to data access. It is composed of up to 61 CPU cores and each core is capable of switching between up to 4 hardware threads on round-robin scheduling, resulting in a total of up to 244 hardware threads available. Each core consists of an slow processor with few extension capabilities (like pentium 4), dual-issue x86 pipeline, a local L1 and L2 cache, and a separate vector processing unit (VPU).

This workshop will focus on a short hands-on to learn how to compile, debug and profile with this architecture, in particular on hybrid computing (OpenMP + MPI).

Ideal Participants

The workshop is focused on intermediate users, and is highly recommended to have working knowledge in Linux/UNIX, MPI and/or OpenMP and one of the programming languages C, C++, Fortran.

We will provide a detailed laboratory to practice during the hands-on, but we encourage to the attendees prepare and bring in their own code to practice rather than simple examples. We are aware that it’s quite easy to run several kind of codes on Intel Xeon Phi, but in order to get performance some changes must to be applied in the code. The perfect code for this workshop is the code that can in hybrid mode (OpenMP + MPI).

eResearch NZ 2013 session type: 

Symposium: 

Submitted by Tim McNamara on